Multidimensional network sorter integrated circuit

ABSTRACT

A technique to implement an integrated multidimensional sorter is to store data such that it may be retrieved in a sorted fashion. Entries are stored into a memory according to time stamp value, and the time stamp value is divided into multiple portions. The memory is organized as a pointer memory. An integrated multidimensional sorter may be implemented using integrated circuit technology using one or more integrated circuits. These integrated circuits may be used in management of network traffic, and provides quality of service (QoS) control.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.11/778,826, filed Jul. 17, 2007, which is a divisional of U.S. patentapplication Ser. No. 10/125,686, filed Apr. 17, 2002 and issued as U.S.Pat. No. 7,284,111 on Oct. 16, 2007, which are incorporated byreference.

BACKGROUND OF THE INVENTION

The present invention relates generally to the field of computer anddata networking, and more particularly, to techniques to moreefficiently process the data packets of a network. Computer networkingis one of the most important technologies in the information age.Personal computers are on the desks of most business people and majorityof homes in the United States, and also becoming more commonplacethroughout the world. Computers are instrumental for facilitatingelectronic commerce and internet traffic. Computers are typicallyconnected using a network that allows the sharing or transfer of databetween computers and devices. This data may include computer files,e-mail, images, audio, video, real-time data, and other types ofinformation. For example, when their computers are joined in a network,people can share files and peripheral such as modems, printers, tapebackup drives, or CD-ROM drives. When networks at multiple locations areconnected, people can send e-mail, share links to the global internet,or conduct videoconferences in real time with other remote users. Localarea network (LANs) are used to connect computers within businesses andhomes. The internet is typically used to connect individual computersand other networks, including local area networks.

Each computer has a set of predefined network ports, which act asmailboxes for incoming and outgoing messages. The ports are typicallyconfigured to support a particular network protocol, and hence toreceive or send a type of packet that is compatible with the protocol.For example, one common port is the UDP (user datagram protocol) port,which provides a channel into the computer for datagram packets that arecommunicated using TCP/IP (transport control protocol/internetprotocol). Datagram packets are sent to a specific UDP port by using aprogramming interface, such as “sockets.” Sockets are a programminginterface originated on Unix operating systems that allows networkcommunication using a file 110 metaphor.

Despite the success of computer networks, there is continuingdevelopment to improve networking technology, especially since networktraffic continues to rapidly grow. For example, it is desirable toincrease transmission speed and network processing speed. This willallow more users to transfer greater amounts of data. Faster processingwill allow better and faster filtering of network traffic so that, forexample, selected users will receive better response times. Further, itis important to improve security on networks, which has increasinglybecome a high priority since the Sep. 11, 2001 terrorist attacks on theWorld Trade Center twin towers in New York City and the Pentagon inWashington, D.C. Better and faster network process will allow betterfiltering to prevent security breaches and transmission of computerviruses.

Integrated circuits are the building blocks of electronic devices andnetworks, including computers, personal digital assistants (PDAs),mobile and other telephony devices, digital cameras and video cameras,digital voice recorders, routers, switches, and network hubs. Some typesof integrated circuit include microprocessors, memories, programmablelogic devices (PLDs), and application specific integrated circuits(ASICs). As integrated circuit technology improves, it becomes possibleto put more and more functionality on single integrated circuits.

As can be appreciated, there is a need for improvements in computernetworking, especially for techniques to improve processing and speed ofprocessing networking information.

BRIEF SUMMARY OF THE INVENTION

The invention provides techniques to implement an integratedmultidimensional sorter where data is stored such that it may beretrieved in a sorted fashion. Entries are stored into a memoryaccording to time stamp value, and the time stamp value is divided intomultiple portions. The memory is organized as a pointer memory. Anintegrated multidimensional sorter may be implemented using integratedcircuit technology using one or more integrated circuits. The techniqueis efficient and allows processing (sorting) of a large amount of data,with minimal impact on throughput of the data through the system. Theseintegrated circuits may be used in management of network traffic, andprovides quality of service (QoS) control.

In an embodiment, the invention is an integrated circuit including Msorter blocks, where each sorter block has a user-selectable number ofentries of one or more entries. Each entry has a time stamp value and aconnection value, there are a total of N entries for all the M sorterblocks, and M is an integer 2 or greater. M may be user-selectable. Whena first sorter block may be configured to have Y entries, there are M−1remaining sorter blocks which have at most a total of (N−Y) entries.When a second sorter block is configured to have Z entries, the sorterblocks, not including the first and second sorter blocks, have at most(N−Y−Z) entries.

In operation, upon receiving a first packet of information on a firstport, a first time stamp and a first connection value are stored in afirst entry of a first sorter. Upon receiving a second packet ofinformation on the first port, a second time stamp and a secondconnection value are a second entry of the first sorter. Upon receivinga third packet of information on a second port, a third time stamp and athird connection value are stored in a first entry of a second sorter.Upon receiving a fourth packet of information on the second port, afourth time stamp and a fourth connection value are stored in a secondentry of the second sorter.

In another embodiment, the invention is an integrated circuit includinga first sorter block portion of the integrated circuit comprising N(1)entries, where each entry includes a connection value and a time stampvalue. Entries in the first sorter block are sorted according to theirtime stamp value, and the number of entries N(1) is user-selectable.

A second sorter block portion of the integrated circuit includes N(2)entries, where each entry includes a connection value and a time stampvalue. Entries in the second sorter block are sorted according to theirtime stamp value, and the number of entries N(2) is user selectable.

In another embodiment, the invention is an integrated circuit includingfirst control circuitry to implement a first sorter block comprisingN(1) entries, where each entry includes a connection value and a timestamp value. Entries in the first sorter block are sorted according totheir time stamp value, and the number of entries N(1) isuser-selectable. Second control circuitry to implement a second sorterblock includes N(2) entries, where each entry comprises a connectionvalue and a time stamp value. Entries in the second sorter block aresorted according to their time stamp value, and the number of entriesN(2) is user-selectable.

In another embodiment, the invention is an integrated circuit includingcontrol circuitry to implement M sorter blocks, where each sorter blockhas a user-selectable number of entries of one or more entries. Eachentry has a time stamp value and a connection value. There are a totalof N entries for all the M sorter blocks, and M is an integer 2 orgreater.

In another embodiment, the invention is a method of receiving a firstentry to be stored in a memory location, where the first entry has atime stamp value and a data value. The time stamp value of the firstentry is divided into two or more portions, a first time stamp portionand a second time stamp portion.

A first pointer memory structure is provided and referenced using afirst pointer address and having a head and a body, where the headcomprises a bit map field and a pointer-to-body field. A second pointermemory structure is provided and referenced using a second pointeraddress and having a head and a body, where the head comprises a bit mapfield and a pointer-to-body field. The second pointer address is storedat a location in the body of the first pointer memory structure based onthe first time stamp portion. The location of the second pointer addressis indicated in the bit map field of the head of the first pointermemory structure.

In another embodiment, the invention includes a method of receiving anentry having a binary time stamp having at least four bits and datavalue. The binary time stamp is divided into a first time stamp portionhaving at least two bits and second time stamp portion having at leasttwo bits.

A first pointer memory structure is provided and referenced using afirst pointer address and having a head and a body, where the head has abit map field with four bits and the body has four memory positions.Each bit in the bit map field represents one of the four memorypositions. The four bits of the head of the first pointer memorystructure are initialized to a first state.

When storing a second pointer address in a first memory position of thefour memory positions, a first bit of the four bits of the head of thefirst pointer memory structure is changed to a second state. Whenstoring the second pointer address in a second memory position of thefour memory positions, a second bit of the four bits of the head of thefirst pointer memory structure is changed to the second state. Whenstoring the second pointer address in a third memory position of thefour memory positions, a third bit of the four bits of the head of thefirst pointer memory structure is changed to the second state. Whenstoring the second pointer address in a fourth memory position of thefour memory positions, a fourth bit of the four bits of the head of thefirst pointer memory structure is changed to the second state.

Other objects, features, and advantages of the present invention willbecome apparent upon consideration of the following detailed descriptionand the accompanying drawings, in which like reference designationsrepresent like features throughout the figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a computer network system within which the presentinvention may be embodied.

FIG. 2 shows a switch or router used to connect a number of ports andconnections to a network.

FIG. 3 shows an integrated circuit or chip with a controller or controlcircuitry portion and memory portion.

FIG. 4 shows a flow diagram of a technique of the invention.

FIG. 5 shows an example of a memory map for a pointer memory.

FIGS. 6A and 6B show a more detailed example of a technique of adding atime entry stamp. FIG. 6A shows the pointers before adding a time stamp.FIG. 6B shows the pointers after adding the time stamp.

FIG. 7 shows a more detailed example of searching for a minimum timeentry stamp.

FIGS. 8A, 8B, 8C, and 8D show four different versions of pointerstructures.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows a computer network system 101 within which the presentinvention may be embodied. There may be any number of servers andclients in the system. For example, there may be thousand or evenmillions of servers and clients. In this system, there are threeservers, server 1, server 2, and server 3, and there are three clients,client 1, client 2, and client 3. The servers communicate with theclients by exchanging packets over a network 120. The computer networksystem is representative of many different environments including a LANsystem, a wide area network (WAN) system, and an internet system.

A network generally includes (1) at least two computers, (2) a networkinterface or network interface card (NIC) on each computer, (3) aconnection medium, and (4) network operating system software. The NIC isa device that lets the computer talk to the network. The connectionmedium is usually a wire or cable, although wireless communicationbetween networked computers and peripherals is also available. Someexamples of network operating systems software include Microsoft Windows95 or Windows NT, Novell NetWare, AppleShare, or Artisoft LANtastic.

Most networks include a hub or switch. Hubs, or repeaters, are simpledevices that interconnect groups of users. Hubs forward any datapackets—including e-mail, word-processing documents, spreadsheets,graphics, print requests—they receive over one port from one workstationto all their remaining ports. All users connected to a single hub orstack of connected hubs are in the same “segment,” sharing the hubbandwidth or data-carrying capacity. As more users are added to asegment, they compete for a finite amount of bandwidth devoted to thatsegment.

Switches are smarter than hubs and offer more dedicated bandwidth tousers or groups of users. A switch forwards data packets only to theappropriate port for the intended recipient, based on information ineach packet header. To insulate the transmission from the other ports,the switch establishes a temporary connection between the source anddestination, and then terminates the connection when the conversation isdone.

A router links a local network to a remote network. On the internet, arouter is a device or, in some cases, software in a computer, thatdetermines the next network point to which a packet should be forwardedtoward its destination. The router is connected to at least two networksand decides which way to send each information packet based on itscurrent understanding of the state of the networks it is connected to. Arouter is located at any gateway (where one network meets another),including each Internet point-of-presence. A router is often included aspart of a network switch.

A router may create or maintain a table of the available routes andtheir conditions and use this information along with distance and costalgorithms to determine the best route for a given packet. Typically, apacket may travel through a number of network points with routers beforearriving at its destination. Routing is a function associated with thenetwork layer (layer 3) in the standard model of network programming,the Open Systems Interconnection (OSI) model. A layer-3 switch is aswitch that can perform routing functions.

FIG. 2 shows a switch or router 202 used to connect a number of portsand connections to a network, such as network 120, using an output link205. ADSL, Ti, and T3 are some examples of types of broadbandconnections. Each port may be allocated for a particular type ofinformation such as video, voice, or data. There are M total ports (mayalso referred to as a sorters in this document) and N total connections(may also be referred to as entries in this document). M and N areintegers. The ports are numbered 1 through M, and the connections arenumbered 1 through N. Each port has a number of connections associatedwith it. Specifically, port I has N(I) connections. So, port 1 has N(1)connections, which is two; port 2 has N(2) connections, which is 3; andport M has N(M) connections.

Each connection or entry stores the information of a packet. Thisconnection data may be held in a memory such as a random access memory(RAM) or pointer memory data structure.

This data includes the packet information and a time stamp of thepacket. The time stamp gives the time that the packet was received. Thepacket information may also be referred to as packet data, connectionvalue, or payload. In operation, many packets are received at a port atdifferent times and these will be stored in entries. The packets in theentries will then be passed out of the port. There are varioustechniques to prioritize which entries are sent out first. Generally,the earlier received packets are sent out first. So, the packets withthe lowest time stamp will be sent out first. The packet with theminimum time stamp has the highest priority. Other priority schemes mayalso be used. For example, in the alternative, the most recentlyreceived packets may be sent out first. In this case, the packets withthe highest time stamp will be sent out first.

To implement such priority schemes, the entries for a particular portare sorted by time stamp to determine which time stamps will be sent outof the port first. To prioritize to send out earliest received entriesfirst, the entries will be sorted so time stamps are from lowest tohighest. Each port is sorted individually, which means the entries forport 1 will be sorted independently of port 2 and the other ports. Andthe entries in port 2 will be sorted independently of port 1 and theother ports. Therefore, each port may be referred to as a sorter becausethe entries associated with a particular sorted are sorted independentlyof the other sorters.

Some sorting techniques are binary tree and heap sort. Other sortingalgorithms may also be used. Sorting the entries will typically takeseveral memory cycles to complete.

In an implementation of the invention, the number of ports orconnections, or both, are user-selectable. For example, a user mayconfigure or program the device to have one port, two ports, threeports, or four ports or more. Furthermore, the user may also configureor program the device to have three connections in the first port, twoconnections for the second port, or any number of connections for aspecific port that is permitted by the design. There are differenttechniques of designing a device to allow for user-configurability. Forexample, a user may configure the device by placing the appropriatesignals at particular pins or by loading the appropriate bits intoflip-flops, registers, storage, or memory cells of the device. Perhapselectrically erasable (EEPROM) or Flash memory cells may be used toallow for nonvolatile storage of the user's configuration. Or static RAM(SRAM) or dynamic RAM (DRAM) cells may be used to allow for volatilestorage of the user's configuration.

There may be any number of connections, which may be user selectable,assigned to each port. For example, port 1 of FIG. 2 is for ADSL 1 videoand has two connections, connection 1 and 2. Port w is for Ti data andhas four connections, connections y, u, g, and z. In an implementation,the total number of connections N may be divided in any desired wayamong the ports. For example, if N is 64K and there are two ports, ifport 1 has 25 connections, then port 2 may have at most 64K-25connections.

Generally, the number of ports a user selects will depend on the numberof devices a user will be using. The number of connections willgenerally be allocated according to bandwidth, where the greaterbandwidth ports will have more connections. For example, a Ti videoconnection has greater bandwidth than an ADSL voice connection, andtherefore will usually have a greater number of connections. As can beappreciated, as N and M increase, the circuitry to implement the sortersand entries becomes more complicated.

Alternatively, in another implementation of the invention, rather thanuser-selectability, a device may be designed with fixed number of portsand connections, and the user may choose to not use all the availableports and connections. In another implementation, the features such asthe number of ports and connections of the device may be configured byselecting the appropriate masks during fabrication. This may be referredto as factory programmability.

The ports (sorters) and connections (entries) may be implemented usingone or more integrated circuits. In one embodiment, the sorters andentries are implemented using a single integrated circuit. FIG. 3 showsan integrated circuit or chip 306 with a controller or control circuitryportion 314 and memory portion 319. The control circuitry is connectedto the memory. The control circuitry implements the sorters and entrieswhile the memory provides the storage for the entries. For example, thecontrol circuitry would implement the user-selectability feature of thenumber of sorters and entries. In an embodiment of the invention, M isat least two, so there are two or more sorters on a single integratedcircuit. The invention may be referred to as an integrated multipledimension sorter (IMDS). The integrated circuit be a PLD or fieldprogrammable gate array (FPGA) or ASIC, or a custom-designed integratedcircuit.

In an alternative implementation, the controller 314 and memory 319 areon separate integrated circuits. Integrated circuits 314 and 319 couldbe connected using traces of a PC board or may be a wire or cable. Theintegrated circuits may be on different electronic boards or even indifferent locations, being connected by a network or modem. The memorymay be, for example, a static RAM (SRAM) or dynamic RAM (DRAM)integrated circuit, a memory integrated with a combination of memorytechnologies. The memory may also be a fixed disk or other magneticstorage, or electrically erasable (EEPROM) storage. However, disk drivetechnology has generally slower access times than integrated circuitmemories and therefore would not be used in a higher performanceimplementation.

FIG. 4 shows a flow diagram of a technique of the invention. Thecontroller circuitry portion of the integrated circuit typically is usedto implement this technique. The controller circuitry may include logicgates, state machines, registers, flip-flops, and others circuit used toimplement logic.

In a step 403, the technique includes receiving a first entry to bestored in a memory location. The first entry has a time stamp value anda connection or data value, and may include other information. Theinformation of the entry may sometimes be referred to as the payload. Ina specific embodiment, this entry is a packet received over the network,and the time stamp is the time which the packet was received. Asdiscussed above, the memory location may be on the same integratedcircuit as the controller or a different integrated circuit.

In a step 407, the first entry will be stored in a position or locationin the memory which is based upon its time stamp value. Any subsequententries, such as second and third entries, will also be stored inpositions or locations in the memory based upon their time stamp values.In an embodiment, the time stamp value is represented as a binary value.However, other implementations, the time stamp value may be representedusing other numbering systems such as octal, decimal, or hexadecimal.Depending on the specific application, the time stamp may be any length.For example, the time stamp may be 4 bits, 6 bits, 8 bits, 16 bits, 24bits, or 32 bits or more.

In a step 412, when storing an entry into the memory, the time stamp isdivided into at least two portions or parts. For example, a 6-bit timestamp value may be divided into two 3-bit portions. A 7-bit time stampvalue may be divided into a 3-bit portion and a 4-bit portion. A 17-bittime stamp value may be divided into a one five 3-bit portions and one2-bit portion. How the time stamp is divided into portions depends onthe length of the time stamp, organization of the memory, speed of thenetwork in transferring packets, and other factors. In general, it isdesirable to optimize the speed at which packets are stored.

In a specific embodiment, the first entry is stored in the memory thatis organized as a pointer memory. A pointer is a reference to anothermemory location. In particular, the pointer stores the address ofanother memory location. In a step 419, there will be a first pointermemory structure. This first pointer memory structure will be referencedusing a first pointer address and will have a head and a body. The headwill have a bit map field and a pointer-to-body field.

In a specific embodiment, the bit map field will have a single binarybit for each memory location in its body. In other embodiments, the bitmap field may be represented in another format, such as octal orhexadecimal digits. Therefore, there will be n binary bits for a bodyhaving n memory locations. For example, if there are eight locations inthe body, the bit map field will have eight bits. And the bit map fieldis used to uniquely identify one of the memory locations of the body.For example, the most significant bit (MSB) of the bit map field may beused to indicate a value is being stored in a first memory locationbody. The least significant bit (LSB) of the bit map field may be usedto indicate a value is being stored in a last memory location (i.e.,location n) of the body. If the MSB is bit 0, then bit 1 may be used toindicate a value is being stored in a second location. Other techniquesfor uniquely representing or identifying memory locations using a bitmap field may be used. For example, the LSB may be used to indicate thefirst memory location, and the MSB used to indicate the last memorylocation.

Generally, the number of bits in the bit map field will be related tohow the time stamp is divided. Specifically, if the time stamp portionhas n bits, then the bit map field to store that time stamp portion willhave 2^n bits and there will also be 2^n memory locations for thepointer structure. For example, if the time stamp field has a 3-bitportion, then the bit map field will have 2^3 or 8 bits.

FIG. 5 shows an example of how the memory is organized (i.e., memorymap) to make a pointer memory. This memory can be SRAM, SDRAM, or evenDRAM. An integrated multidimensional sorter may be implemented using anykind of memory technology. There is a section 505 of the memoryallocated for heads of the pointers, a section 508 for bodies of thepointers, a section 513 for free list, and a section 520 for aconnection value or flow ID (FID) list. In this figure, three differentpointer heads are represented by head1, head2, and head3. Threedifferent pointers to bodies are represented by body1, body2, and body3.Three different free lists are represented by free list1, free list2,and free list3. There is one connection value or FID list; however, inother embodiments, there may be a two or more connection value or FIDlists (flow ID list).

Returning to FIG. 4, in a step 425, a second pointer memory structure isprovided. The second pointer memory structure is similar to thatdiscussed above for the first pointer memory structure. However the bitmap field for the second pointer memory structure may or may not havethe same number of the bits as the first pointer memory structure. Thereason is similar to that discussed above for how the time stamp fieldmay be divided into portions that have any number of bits. The secondpointer memory structure is referenced using a second pointer addressand has a head and a body. The head has a bit map field and apointer-to-body field. As indicated by a step 429, the second pointeraddress is stored at a location in the body of the first pointer memorystructure based on the first time stamp portion.

In step 433, as was discussed above, the location of the second pointeraddress is indicated in the bit map field of the head of the firstpointer memory structure.

The steps above are for storing a single portion of a time stamp intomemory. The technique may be extended to have as many steps (similar tosteps 419 to 433 repeated) and pointers as needed to store an entry intothe memory. So, to store a second portion of the time stamp into memory,there would be an additional step of storing a third pointer address ata location in the body of the second pointer memory structure based onthe second time stamp portion. And, there would be a step to store at amemory location referenced by the third pointer address the data value.

The technique of FIG. 4 merely illustrates the flow of one particularimplementation of the invention. As one of skill in the art willrecognize, there are many possible variations and alternatives of theapproach described in above, and any of these variations may be used.

After entries are stored using the above flow, they may be easilyretrieved in out of the memory according to a sorted order. For example,the entries may be retrieved by minimum or lowest time stamp or maximumor greatest time stamp. A more detailed example of retrieving an entrywith a specific time entry stamp is discussed below.

This invention provides a technique of searching or sorting information.Assume for some application, we need to have M sorters to sort Nentries' values, which we can call “time stamp” or “TS.” For example,sorter 1 can sort N_1 time stamps, sorter 2 can sort N_2 time stamps,sorter 3 can sort N_3 time stamps, and so forth. Therefore, sorter M cansort N_M time stamps. N_1+N_2+N_3+ . . . +N_M=N. However, each sortercan also sort up to N time stamps. For example, N_1=N while N_2=N_3= . .. N_M=0.

As the example shown above, the goal of this invention is to build anintegrated sorter in one single data structure. The requirements are asfollows. (1) M sorters, which can call “ports.” (2) Each port can sort(or search the minimum or maximum TS) up to N time stamps. (3) Eachsorter's TS cannot be mixed with other sorter's TS.

For single sorter, people use binary tree or heap algorithms to sort.For example, to sort 256 time stamps, if using radix=2 (where eachbinary tree node compares 2 TS), it takes 8 comparisons (since 2^8=256)to find the minimum or maximum TS. If using radix=4 (where each binarytree node compares 4 TS), it takes 4 comparisons (since 4^4=256) to findthe minimum or maximum TS.

For a multiple dimensional sorter, there are no good existing solutions.A straightforward approach is to duplicate the approaches used for asingle sorter,

Existing solutions are not good enough. As explained above, no existingsorting schemes can be implemented in an efficient way, the maindrawbacks are as follows. They require expensive hardware (e.g., manycomparators). The design cannot be scaled up because there is a need toduplicate from single sorter to become multiple sorters. There needs tobe at least O(log N) operations to find the minimum or maximum TS, whereN is the number of TS needs to be sort.

This application provides a brief description of the invention andincludes a discussion of how it accomplishes what it does. Thisapplication has examples and drawings. This novel sorting scheme isbased on follows concepts: (1) Break each time stamp to pieces:

Each piece represents several bits of time stamp. For example, a given wbits wide time stamp can be chopped into v pieces, TS (w)=TS_1(w_1) &TS_2(w_2) & . . . & TS_v(w_v), where & means concatenate.

TS_1 has w_1 bits. Its first bit is the most significant bit (MSB) ofthe whole time stamp (or the LSB if so desired). TS_2 has w_2 bits, andso on. Note that w_1+w_2+ . . . +w_v=w. The values of each w_x can beany value, as long as the sum of all w_x(x@[1 . . . v]) is w.

Each TS layer is composed of a head and body. The head has two parts,bit map and pointer_to_body (PB). The bit map has 2^w_x bits (x is thelayer number). Each bit represents the status of the correspondingpointer in the body. For example, if bit 12 is asserted, then pointer 12in the body is a valid pointer. Note that the bit map can also bedecoded or compressed, but this may require more logic to handle thedecoding or compression. For an integrated circuit embodiment, thiswould add additional circuitry and would increase the die size, which isgenerally undesirable.

The PB can be used as memory pointer to the body of that TS layer (ifthe two are separate). The body contains the pointers to the next TSlayer. Note that the head and body can be combined to one block orseparated (e.g., two or more different memory locations). Each TS'spieces will be decoded and then populated in its corresponding TS layer.

FIGS. 6A and 6B show a more detailed example of a technique of adding atime entry stamp. FIGS. 6A and 6B show an example of a 7-bit TS,TS=“1O1O111.” FIG. 6A shows the pointers before adding this time stamp.FIG. 6B shows the pointers after adding this time stamp.

Let us choose w_1=3, w_2=2, W_3=2. Therefore, TS_1 is 3 bits, and equalto “101.” TS_2 is 2 bits, and equal to “01.” TS_3 is 2 bits, and equalto “11.” TS_1's bit map is 8 bits (2^3=8), and contains 8 pointers inbody, while TS_2 and TS_3's bit map is 4 bits (2^2=4), and contains2^2=4 pointers in body.

FIGS. 6A and 6B show an example of adding a TS entry. The operations areas follows.

Operations on the first layer (TS_1): Use the port number i as a pointerto find the bit map and PB (pointer_to_body) in the head of first TSlayer. Decode “101” as 5.

Case A: If bit_5 location in the bit map is 1, that means there isanother TS entry with the same TS_1 value, i.e., TS_i=“101.” Use PB+5 asthe address to read out pointer in body. This is the pointer to next TSlayer.

Case B: If bit_S location in the bit map is 0, that means no other TSentry has the same TS_1 value. In this case, we need to add TS to thesorter starting from the current layer. We need to get a pointer (e.g.,pt_b in FIG. 6B) from free list (see memory map of FIG. 5), and use PB+5as the address to store it in body, this is the pointer to next TSlayer. Finally we need to set the bit_S location in the bit map to 1 toindicate there is a corresponding TS entry whose TS_1 is “101.”

Operations on the second layer (TS_2): Use the pt_b as address to findthe bit map and PB (pointer_to_body) in the head of second TS layer.Decode “01” as 1.

Case A: If bit_1 location in the bit map is 1, that means there isanother TS entry with the same TS_2 value, i.e., TS_2=“01.” Use PB+1 asthe address to read out pointer in body. This is the pointer to next TSlayer.

Case B: If bit_1 location in the bit map is 0, that means no other TSentry has the same TS_2 value. In this case we need to add TS to thesorter, starting from the current layer. We need to get a pointer (e.g.,pt_d in FIG. 6B) from free list, and use PB+1 as the address to store itin body, this is the pointer to next TS layer. Finally we need to setthe bit_1 location in the bit map to 1, to indicate there is acorresponding TS entry whose TS_2 is “01.”

Use the port number i as a pointer to find the bit map and PB(pointer_to_body) in the head of first TS layer. Decode “11” as 3.

Case A: If bit_3 location in the bit map is 1, that means there isanother TS_3 entry with the same TS_3 value, i.e., TS_3=“11.” Use PB+3as the address to read out pointer in body. This is the pointer to nextTS layer.

Case B: If bit_3 location in the bit map is 0, that means no other TSentry has the same first TS_3 value. We need to get a pointer (e.g.,pt_g in FIG. 6B) from free list, and use PB+3 as the address to store itin body, this is the pointer to next TS layer. Finally we need to setthe bit_3 location in the bit map to 1, to indicate there is acorresponding TS entry whose TS_1 is “11.” The adding procedure is nowcompleted.

Returning to FIG. 5, specifically, there are 3 TS pieces, TS_1, TS_2,and TS_3. Each piece has Head and Body. Besides, we have individual FreeList to maintain the pointer (if the bit map of Head in that TS piece is0, we will get a pointer from Free List, and store it back to the bodyusing (PB (pointer to body)+bit_location as address)). Finally, we haveFID list (Flow ID list) to maintain connection (or Flow ID) Link List.Different connections with same TS will associated by the link list.

FIG. 7 shows a more detailed example of searching for a minimum timeentry stamp. The data flow is indicated by arrows 705, 708, 711, 714,717, 710, and 723. The result is shown by box 726. Although this exampleshows searching for a minimum time stamp, a maximum time stamp may besearched for using a similar technique. More specifically, instead ofstarting with the MSB, start at the LSB first.

When searching minimum TS, the operations are as follows. Use the portnumber i as a pointer to find the bit map and PB (pointer_to_body) inthe head of first TS layer. Find the first_non-zero_bit_location. UsePB+first_non-zero_bit_location as the address to read out pointer inbody. This is the pointer to next TS layer. In the example, thefirst_non-zero_bit_location is “001,” and the corresponding pointer ispt_a.

Use the pt_a as address to find the bit map and PB (pointer_to_body) inthe head of second TS layer. Find the first_non-zero_bit_location. UsePB+first_non-zero_bit_location as the address to read out pointer inbody. This is the pointer to next TS layer. In the example, thefirst_non-zero_bit_location is “11,” and the corresponding pointer ispt_c.

Use the pt_c as address to find the bit map and PB (pointer_to_body) inthe head of third TS layer. Find the first_non-zero_bit_location. UsePB+first_non-zero_bit_as the address to read out pointer in body. Thisis the pointer to next TS layer. In the example, thefirst_non-zero_bit_location is “10,” and the corresponding pointer ispt_e.

As a result of these operations, the minimum TS can be found based on“001” & “11” & “10” or “0011110,” where & represents concatenation.

FIGS. 8A, 8B, 8C, and 8D show four different versions of pointerstructures which may be used to implement the invention. Depending onthe particular implementation or application, each version has somespecial benefits. As described above, a time stamp (TS) pieces has twoparts, head and body. These can be combined to have one part or separateparts. To illustrate this concept clearly, FIGS. 8A, 8B, 8C, and 8D showfour versions of head and body structures that may be implemented.

FIG. 8A shows version 1. The head and body are combined into one part,so there is no need for a pointer to point to the body location.

FIG. 8B shows version 2. This version has separate head and body. Apointer (PB) to point to the body location is needed.

FIG. 8C shows version 3. This version also has separate head and body.There is a special pointer called PBmin which points to the locationwhich has first valid pointer existing in the body.

FIG. 8D shows version 4. This version also has separate head and body.There are two pointers in the head, PB and PM. The PB pointer points tofirst location of the body. The PM pointer which value equals to firstvalid pointer in the body. For example, in FIG. 8D, PM=Pt_a.

This description of the invention has been presented for the purposes ofillustration and description. It is not intended to be exhaustive or tolimit the invention to the precise form described, and manymodifications and variations are possible in light of the teachingabove. The embodiments were chosen and described in order to bestexplain the principles of the invention and its practical applications.This description will enable others skilled in the art to best utilizeand practice the invention in various embodiments and with variousmodifications as are suited to a particular use. The scope of theinvention is defined by the following claims.

1. An integrated circuit comprising: M sorter blocks, wherein eachsorter block has a user-selectable number of entries of one or moreentries, each entry comprises a time stamp value and a connection value,there are a total of N entries for all the M sorter blocks, and M is aninteger 2 or greater, each sorter block comprises a pointer memorystructure, referenced using a first pointer address having a head and abody, wherein the head comprises a bit map field comprising four bitsand the body comprises four memory positions, each bit in the bit mapfield representing one of the four memory positions, when storing asecond pointer address in a first memory position of the four memorypositions, changing a first bit of the four bits of the head of thefirst pointer memory structure to a second state from a first state,when storing the second pointer address in a second memory position ofthe four memory positions, changing a second bit of the four bits of thehead of the first pointer memory structure to the second state, whenstoring the second pointer address in a third memory position of thefour memory positions, changing a third bit of the four bits of the headof the first pointer memory structure to the second state, and whenstoring the second pointer address in a fourth memory position of thefour memory positions, changing a fourth bit of the four bits of thehead of the first pointer memory structure to the second state from thefirst state.
 2. The integrated circuit of claim 1 wherein M isuser-selectable.
 3. The integrated circuit of claim 2 wherein when asecond sorter block is configured to have Z entries, the sorter blocks,not including the first and second sorter blocks, have at most (N−Y−Z)entries.
 4. The integrated circuit of claim 1 wherein when a firstsorter block is configured to have Y entries, there are M−1 remainingsorter blocks which have at most a total of (N−Y) entries.
 5. Theintegrated circuit of claim 1 wherein upon receiving a first packet ofinformation on a first port, storing a first time stamp and a firstconnection value in a first entry of a first sorter, upon receiving asecond packet of information on the first port, storing a second timestamp and a second connection value in a second entry of the firstsorter, upon receiving a third packet of information on a second port,storing a third time stamp and a third connection value in a first entryof a second sorter, and upon receiving a fourth packet of information onthe second port, storing a fourth time stamp and a fourth connectionvalue in a second entry of the second sorter.
 6. The integrated circuitof claim 5 wherein the first and second entries placed in the firstsorter are sorted according to the first and second time stamps, and thethird and fourth entries placed in the second sorter are sortedaccording to the third and fourth time stamps.
 7. The integrated circuitof claim 6 wherein the first and second entries are sorted so an entrywith an earlier time stamp is placed before the entry with a later timestamp.
 8. An integrated circuit comprising: a first sorter block portionof the integrated circuit comprising N(1) entries, wherein each entrycomprises a connection value and a time stamp value, entries in thefirst sorter block are sorted according to their time stamp value, andthe number of entries N(1) is user-selectable; and a second sorter blockportion of the integrated circuit comprising N(2) entries, wherein eachentry comprises a connection value and a time stamp value, entries inthe second sorter block are sorted according to their time stamp value,and the number of entries N(2) is user selectable, wherein the secondsorter block comprises a first pointer memory structure, referencedusing a first pointer address and having a head and a body, wherein thehead comprises a bit map field comprising n bits and the body comprisesn memory positions, each bit in the bit map field representing one ofthe n memory positions, wherein n is an integer, upon receiving a firsttime stamp value for a first entry for the second sorter block, dividingthe first time stamp value into at least a first portion and a secondportion, wherein the first portion has n bits and the second portion hasm bits, wherein m is an integer, storing a second pointer address at amemory position in the body of the first pointer memory structurecorresponding to the first portion of the first time stamp value, andchanging a bit in the bit map field of the head of the first pointermemory structure corresponding to the memory position in the body of thefirst pointer memory structure corresponding to the first portion of thefirst time stamp value.
 9. The integrated circuit of claim 8 whereineach entry in the first sorter block is placed at a location based onits time stamp value, and each entry in the second sorter block isplaced at a location based on its time stamp value.
 10. The integratedcircuit of claim 8 wherein the entries are stored in a random accessmemory portion of the integrated circuit.
 11. The integrated circuit ofclaim 8 wherein the first sorter block comprises a second pointer memorystructure, referenced using a second pointer address and having a headand a body, wherein the head comprises a bit map field comprising q bitsand the body comprises q memory positions, each bit in the bit map fieldrepresenting one of the q memory positions, wherein q is an integer. 12.An integrated circuit comprising: first control circuitry to implement afirst sorter block comprising N(1) entries, wherein each entry comprisesa connection value and a time stamp value, entries in the first sorterblock are sorted according to their time stamp value, and the number ofentries N(1) is user-selectable; and second control circuitry toimplement a second sorter block comprising N(2) entries, wherein eachentry comprises a connection value and a time stamp value, entries inthe second sorter block are sorted according to their time stamp value,and the number of entries N(2) is user-selectable, wherein the firstcontrol circuitry comprises a first pointer memory structure, referencedusing a first pointer address and having a head and a body, wherein thehead comprises a bit map field comprising n bits and the body comprisesn memory positions, each bit in the bit map field representing one ofthe n memory positions, wherein n is an integer, upon receiving a firsttime stamp value for a first entry for the first control circuitryblock, dividing the first time stamp value into at least a first portionand a second portion, wherein the first portion has n bits and thesecond portion has m bits, wherein m is an integer, storing a secondpointer address at a memory position in the body of the first pointermemory structure corresponding to the first portion of the first timestamp value, and changing a bit in the bit map field of the head of thefirst pointer memory structure corresponding to the memory position inthe body of the first pointer memory structure corresponding to thefirst portion of the first time stamp value.
 13. The integrated circuitof claim 12 wherein the entries for the first and second sorter blocksare stored in another integrated circuit comprising random accessmemory.
 14. The integrated circuit of claim 12 wherein each entry in thefirst sorter block is placed at a location based on its time stampvalue, and each entry in the second sorter block is placed at a locationbased on its time stamp value.
 15. The integrated circuit of claim 12wherein the second control circuitry comprises a second pointer memorystructure, referenced using a second pointer address and having a headand a body, wherein the head comprises a bit map field comprising q bitsand the body comprises q memory positions, each bit in the bit map fieldrepresenting one of the q memory positions, wherein q is an integer.